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1998 preliminary product information mos integrated circuit m pd178046, 178048 document no. u13183ej1v0pm00 (1st edition) date published june 1998 n cp(k) printed in japan 8-bit single-chip microcontroller description the m pd178046 and 178048 are 8-bit single-chip cmos microcontrollers with hardware for digital tuning systems. employing the 78k/0 architecture as the cpu, these microcontrollers provide easy control access to the internal memories and peripheral hardware. the instructions are high-speed 78k/0 instructions suitable for system control. as the peripheral hardware, an osd (on-screen display) controller and pwm (pulse width modulation) output for tv use, as well as many i/o ports, timers, a/d converter, serial interface, and power-on clear circuit are provided. a flash memory model, m pd178f048, that can operate on the same supply voltage as the mask rom models, and many development tools are under development. the functions of these microcontrollers are described in detail in the following users manuals. be sure to read these manuals when you design your system. m pd178048 subseries users manual : planned to be published 78k/0 series users manual - instruction : u12326e features ? rom and ram capacities item program memory character rom data memory video ram (rom) (crom) internal high-speed internal expansion (vram) part number ram ram m pd178046 48k bytes 6912 bytes 512 bytes 512 bytes 482 bytes (12 24 m pd178048 60k bytes (256 characters) characters max.) ? instruction cycle: 0.4 m s (with 5.0-mhz crystal resonator) ? many peripheral hardware circuits general-purpose i/o ports, a/d converter, serial interface, timers, power-on clear circuit ? osd controller and pwm output ? vectored interrupts: 17 ? supply voltage: v dd = 4.5 to 5.5 v the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production.
m pd178046, 178048 2 preliminary product information application field tv ordering information part number package m pd178046cw- 64-pin plastic shrink dip (750 mil) m pd178048cw- 64-pin plastic shrink dip (750 mil) remark indicates rom code suffix. the rom code suffix is e when an i 2 c bus is used.
m pd178046, 178048 preliminary product information 3 development of m pd178048 subseries products under development pd178f048 64 pins osd controller: pwm output: 8-bit resolution 4 channels flash memory: 60 kb ram: 1 kb 256 types 12 lines 24 digits 12 18 dots 8 colors pd178048 flash memory model mask rom models 64 pins rom: 60 kb ram: 1 kb pd178046 64 pins rom: 48 kb ram: 1 kb m m m
m pd178046, 178048 4 preliminary product information function outline (1/2) part number m pd178046 m pd178048 item internal rom 48k bytes 60k bytes memory character rom (crom) 6912 bytes (256 characters) high-speed ram 512 bytes expansion ram 512 bytes video ram (vram) 432 bytes (12 24 characters max.) general-purpose register 8 bits 32 registers (8 bits 8 bits 4 banks) minimum instruction execution time 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (with 5.0-mhz crystal resonator) instruction set 16-bit operation multiplication/division (8 bits 8 bits, 16 bits ? 8 bits) bit manipulation (set, reset, test, boolean operation) bcd adjustment, etc. i/o ports total : 46 pins cmos input : 4 pins cmos i/o : 37 pins n-ch open-drain output : 5 pins a/d converter 8-bit resolution 4 channels serial interface i 2 c bus mode note : 2 channels (shift register: 1 channel) 3-wire serial i/o mode : 1 channel timer basic timer (timer carry (10 hz)) : 1 channel 8-bit timer/event counter : 1 channel 8-bit timer : 1 channel 8-bit event counter : 1 channel 8-bit remote control timer : 1 channel watchdog timer : 1 channel note if the i 2 c bus mode is used (including when it is implemented in software without using the peripheral hardware), inform nec when you order a mask.
m pd178046, 178048 preliminary product information 5 (2/2) part number m pd178046 m pd178048 item pwm output 8-bit resolution 4 channel 14-bit resolution 1 channel osd number of display characters 288 characters max. per screen (12 lines 24 digits) controller character type 256 types (stored in crom) character format 12 (width) 18 (height) dots character size 1 1, 2 2, 3 3, or 4 4 selectable character color 8 colors character frame framed or non-framed characters selected in screen units background no background, blank, or filled selectable. background color (8 colors) can be specified. half blanking can be specified in character units. rom correction 2 places vectored maskable internal: 11, external: 5 interrupt non-maskable internal: 1 source software 1 standby function halt mode stop mode reset reset by reset pin internal reset by watchdog timer reset by power-on clear circuit detection of less than 4.5 v note (during cpu operation and on power application) detection of less than 2.5 v note (in stop mode) supply voltage v dd = 4.5 to 5.5 v package 64-pin plastic shrink dip (750 mil) note these values are the maximum values. actually, reset is effected at lower voltages.
m pd178046, 178048 6 preliminary product information pin configuration (top view) 64-pin plastic shrink dip (750 mil) m pd178046cw- m pd178048cw- cautions 1. directly connect ic (internally connected) pins to gnd0 or gnd1. 2. keep the voltage at the v dd port pin the same as the v dd pin. 3. keep the voltage at the gndport pin the same as gnd0 or gnd1. ic p47 p46 p45 p44 p43 p42 p41 p40 p67 p66 p65 p64 p63 p62 p61 p60 v dd port p54 p53 p52 p51 p50 gndport ti9/p77 to5/p76 ti5/p75 oscmon/p74 ti21/p73 sck3/p72 so3/p71 si3/p70 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v dd p130/pwm00 p131/pwm01 p132/pwm02 p133/pwm03 p134/pwm1 p20/scl0 p21/scl1 p22/sda0 p23/sda1 h sync v sync blank b g r i gnd1 osc1 osc2 p00/intp0 p01/intp1 p02/intp2 p03/intp3 p10/ani0 p11/ani1 p12/ani2 p13/ani3 reset x1 x2 gnd0
m pd178046, 178048 preliminary product information 7 pin names ani0-ani3 : a/d converter input b : character signal output blank : blanking signal output g : character signal output gnd0, gnd1 : ground gndport : port ground h sync : horizontal sync signal input i : character signal output ic : internally connected intp0-intp3 : interrupt input osc1, osc2 : lc connection for osd dot clock oscillation oscmon : osd clock output p00-p03 : port 0 p10-p13 : port 1 p20-p23 : port 2 p40-p47 : port 4 p50-p54 : port 5 p60-p67 : port 6 p70-p77 : port 7 p130-p134 : port 13 pwm00-pwm03 : 8-bit pwm output pwm1 : 14-bit pwm output r : character signal output reset : reset input sck3 : serial clock input/output scl0, scl1 : serial clock input/output sda0, sda1 : serial data input/output si3 : serial data input so3 : serial data output ti5, ti9, ti21 : 8-bit timer clock input to5 : 8-bit timer output v dd : power supply v dd port : port power supply v sync : vertical sync signal input x1, x2 : crystal resonator connection for system clock oscillation
m pd178046, 178048 8 preliminary product information block diagram remark the internal rom capacity differs depending on the model. 8-bit timer /event counter (tm5) port0 serial interface3 (sio3) interrupt control on screen display controller video ram [432 bytes] 8-bit remote controller timer (tm9) 8-bit timer (tm20) watchdog timer 8-bit event counter (tm21) basic timer (btm1) i 2 cbus1 (iic1) character rom [6912 bytes] ti5/p75 p00-p03 to5/p76 ti9/p77 ti21/p73 sda0/p22 sda1/p23 scl0/p20 scl1/p21 r g b i blank h sync v sync osc1 osc2 oscmon/p74 si3/p70 so3/p71 sck3/p72 intp0/p00- intp3/p03 p10-p13 port2 p20-p23 port4 p40-p47 port5 p50-p54 port6 p60-p67 port7 p70-p77 p130-p134 a/d converter ani0/p10- ani3/p13 8-bit pwm (pwm0) pwm00/p130- pwm03/p133 14-bit pwm (pwm1) pwm1/p134 reset x1 x2 v dd port gndport v dd reset cpu peripheral voltage regulator gnd0 gnd1 ic 4 ram [1k bytes] 78k/0 cpu core rom 4 4 4 8 5 8 8 5 4 4 system control port13 port1
m pd178046, 178048 preliminary product information 9 table of contents 1. pin functions ........................................................................................................................... 10 1.1 port pins ............................................................................................................................... 10 1.2 pins other than port pins ................................................................................................. 11 1.3 i/o circuits of respective pins and recommended connection of unused pins .... 12 2. memory space .......................................................................................................................... 15 2.1 memory size select register (ims) .................................................................................. 16 2.2 internal expansion ram size select register (ixs) ...................................................... 17 3. features of peripheral hardware functions ........................................................ 18 3.1 ports ............................................................................................................................... ....... 18 3.2 clock generation circuit ................................................................................................... 19 3.3 timers ............................................................................................................................... .... 19 3.4 a/d converter ...................................................................................................................... 22 3.5 serial interface .................................................................................................................... 23 3.6 osd controller .................................................................................................................... 24 3.7 pwm output ......................................................................................................................... 25 4. interrupt function ............................................................................................................... 26 5. rom correction ..................................................................................................................... 28 6. standby function .................................................................................................................. 29 7. reset function ....................................................................................................................... 29 8. instruction set ...................................................................................................................... 30 9. package drawing ................................................................................................................... 33 appendix a. development tools ........................................................................................... 34 appendix b. related documents .......................................................................................... 36
m pd178046, 178048 10 preliminary product information 1. pin functions 1.1 port pins pin name i/o function at reset shared with: p00-p03 i/o port 0. input intp0-intp3 4-bit i/o port. can be set in input or output mode in 1-bit units. p10-p13 input port 1. input ani0-ani3 4-bit input port. p20, p21 i/o port 2. input scl0, scl1 4-bit i/o port. p22, p23 can be set in input or output mode in 1-bit units. sda0, sda1 p40-p47 i/o port 4. input ? 8-bit i/o port. can be set in input or output mode in 1-bit units. p50-p54 i/o port 5. input ? 5-bit i/o port. can be set in input or output mode in 1-bit units. p60-p67 i/o port 6. input ? 8-bit i/o port. can be set in input or output mode in 1-bit units. p70 i/o port 7. input si3 p71 8-bit i/o port. so3 p72 can be set in input or output mode in 1-bit units. sck3 p73 ti21 p74 oscmon p75 ti5 p76 to5 p77 ti9 p130-p133 output port 13. ? pwm00-pwm03 5-bit output port. p134 n-ch open-drain output port (5 v withstand voltage). pwm1
m pd178046, 178048 preliminary product information 11 1.2 pins other than port pins pin name i/o function at reset shared with: intp0-intp3 input external maskable interrupt input whose valid edge can be input p00-p03 specified (rising edge, falling edge, or both rising and falling edges) si3 input serial data input to serial interface input p70 so3 output serial data output from serial interface input p71 sda0, sda1 i/o serial data input/output to/from n-ch open-drain i/o input p22, p23 serial interface sck3 i/o serial clock input/output to/from serial interface input p72 scl0, scl1 i/o n-ch open-drain i/o input p20, p21 ti5 input external count clock input to 8-bit timer/event counter (tm5) input p75 ti9 external count clock input to 8-bit remote control timer (tm9) p77 ti21 external count clock input to 8-bit event counter (tm21) p73 to5 output 8-bit timer/event counter (tm5) output input p76 ani0-ani3 input analog input to a/d converter input p10-p13 pwm00- output 8-bit pwm output n-ch open-drain i/o ? p130-p133 pwm03 pwm1 14-bit pwm output p134 oscmon output osd clock output input p74 v sync input osd vertical sync signal input input ? h sync osd horizontal sync signal input ? r output red output for osd characters and background low-level ? g green output for osd characters and background output ? b blue output for osd characters and background ? i character background output for osd characters and blank ? background mode blank osd blanking signal output ? reset input system reset input ? ? x1 input crystal resonator connection for system clock oscillation ? ? x2 ? ?? osc1 input lc connection for osd dot clock oscillation ? ? osc2 output ?? v dd ? positive power supply ? ? gnd0, gnd1 ? ground ? ? v dd port ? port power supply ? ? gndport ? port ground ? ? ic ? internally connected. directly connect this pin to gnd0 or gnd1. ? ?
m pd178046, 178048 12 preliminary product information 1.3 i/o circuits of respective pins and recommended connection of unused pins table 1-1 shows the i/o circuit type of each pin and the recommended connection of unused pins. for the configuration of each i/o circuit, refer to figure 1-1 . table 1-1. i/o circuits of respective pins and recommended connection of unused pins pin name i/o circuit type i/o recommended connection of unused pins p00/intp0-p03/intp3 8 i/o set in general-purpose input port mode by software, and individually connect to gnd0, gnd1, or gndport via resistor. p10/ani0-p13/ani3 25 input individually connect to v dd , v dd port, gnd0, gnd1, and gndport via resistor. p20/scl0, p21/scl1 10-d i/o set in general-purpose input port mode by software, and individually p22/sda0, p23/sda1 connect to v dd , v dd port, gnd0, gnd1, or gndport via resistor. p40-p47 5 p50-p54 p60-p67 p70/si3 5-k p71/so3 5 p72/sck3 5-k p73/ti21 p74/oscmon 5 p75/ti5 5-k p76/to5 5 p77/ti9 5-k p130/pwm00 19 output set to low-level output by software and leave unconnected. -p133/pwm03 p134/pwm1 v sync 2 input individually connect to gnd0 or gnd1 via resistor. h sync r 3 output set osd display to off by software and leave unconnected. g b i blank reset 2 input ? osc1 28 input set lc oscillation to off by software and leave unconnected. osc2 output leave unconnected. ic ? ? directly connect to gnd0 or gnd1.
m pd178046, 178048 preliminary product information 13 figure 1-1. i/o circuits of respective pins (1/2) remark v dd and gnd are positive power supply and ground pins for ports. take them as v dd port and gndport. type 3 type 5-k type 2 type 8 type 5 type 10-d schmitt trigger input with hysteresis characteristics in p-ch out data v dd n-ch data output disable p-ch in/out v dd n-ch data output disable p-ch in/out v dd n-ch input enable input enable data output disable p-ch in/out v dd n-ch data output disable p-ch in/out v dd n-ch input enable open drain
m pd178046, 178048 14 preliminary product information figure 1-1. i/o circuits of respective pins (2/2) remark v dd and gnd are positive power supply and ground pins for ports. take them as v dd port and gndport. type 25 input enable comparator + e n-ch p-ch v ref (threshold voltage) type 28 type 19 out n-ch p-ch n-ch p-ch n-ch p-ch v dd v dd n-ch in out n-ch p-ch n-ch
m pd178046, 178048 preliminary product information 15 2. memory space figure 2-1 shows the memory map of the m pd178046 and 178048. figure 2-1. memory map notes 1. the internal rom capacity differs depending on the model (refer to the table below). part number internal rom end address nnnnh m pd178046 bfffh m pd178048 efffh 2. crom cannot be read by software. 3. vram can be written via sfr. cannot be used data memory space program memory space callt table area vector table area f f f f h f f 0 0 h f e f f h f e e 0 h f e d f h f 8 0 0 h f 7 f f h f 6 0 0 h f 5 f f h f d 0 0 h f c f f h n n n n h + 1 n n n n h n n n n h 1 0 0 0 h 0 f f f h 0 8 0 0 h 0 7 f f h 0 0 8 0 h 0 0 7 f h 0 0 4 0 h 0 0 3 f h 0 0 0 0 h 0 0 0 0 h cannot be used program area callf entry area program area special function register (sfr) 256 8 bits general-purpose register 32 8 bits internal high-speed ram 512 8 bits internal expansion ram 512 8 bits internal rom note 1 crom note 2 (6912 byte) vram note 3 (432 byte)
m pd178046, 178048 16 preliminary product information 2.1 memory size select register (ims) the internal memory capacities can be changed by using the memory size select register (ims). set ims to the value shown in table 2-1 depending on the internal memory capacity of each model. use an 8-bit memory manipulation instruction to set this register. ims is set to cfh at reset. figure 2-2. format of memory size select register (ims) ram2 ram1 ram0 selects internal high-speed ram capacity 0 1 0 512 bytes others setting prohibited ram3 ram2 ram1 ram0 selects internal rom capacity 1100 48k bytes 1111 60k bytes others setting prohibited table 2-1. set value of memory size select register (ims) part number set value of ims m pd178046 4ch m pd178048 4fh 7 ram2 6 ram1 5 ram0 4 0 3 rom3 2 rom2 1 rom1 0 rom0 symbol ims address fff0h at reset cfh r/w r/w
m pd178046, 178048 preliminary product information 17 2.2 internal expansion ram size select register (ixs) the internal expansion ram capacity can be selected by using the internal expansion ram size select register. this register of the m pd178046 and 178048 must be set to 0bh. use an 8-bit memory manipulation instruction to set ixs. the value of this register is set to 0ch at reset. figure 2-3. format of internal expansion ram size select register (ixs) ixram4 ixram3 ixram2 ixram1 ixram0 selects internal expansion ram capacity 01011 512 bytes others setting prohibited 7 0 6 0 5 0 4 ixram4 3 i xram3 2 i xram2 1 i xram1 0 i xram0 symbol ixs address fff4h at reset 0ch r/w r/w
m pd178046, 178048 18 preliminary product information 3. features of peripheral hardware functions 3.1 ports the following three types of i/o ports are available: cmos input (port 1) : 4 pins cmos i/o (ports 0 and 2 through 7) : 37 pins n-ch open-drain output (port 13) : 5 pins total : 46 pins table 3-1. port functions name pin name function port 0 p00-p03 i/o port. can be set in input or output mode in 1-bit units. port 1 p10-p13 input port port 2 p20-p23 i/o port. can be set in input or output mode in 1-bit units. port 4 p40-p47 i/o port. can be set in input or output mode in 1-bit units. port 5 p50-p54 i/o port. can be set in input or output mode in 1-bit units. port 6 p60-p67 i/o port. can be set in input or output mode in 1-bit units. port 7 p70-p77 i/o port. can be set in input or output mode in 1-bit units. port 13 p130-p134 n-ch open-drain output port
m pd178046, 178048 preliminary product information 19 3.2 clock generation circuit the instruction execution time can be changed as follows: 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (system clock: 5.0-mhz crystal resonator) figure 3-1. block diagram of clock generation circuit 3.3 timers six timer channels are provided. basic timer : 1 channel 8-bit timer/event counter : 1 channel 8-bit timer : 1 channel 8-bit event counter : 1 channel 8-bit remote control timer : 1 channel watchdog timer : 1 channel figure 3-2. block diagram of basic timer (btm1) f x x1 x2 system clock oscillation circuit prescaler selector prescaler standby control circuit clock to peripheral hardware other than above cpu clock (f cpu ) stop f x 2 f x 2 2 f x 2 3 f x 2 4 wait control circuit divider intbtm1 5.0 mhz btmsel selector basic timer 1 mode register (btmmd1) internal bus
m pd178046, 178048 20 preliminary product information figure 3-3. block diagram of 8-bit timer/event counter (tm5) figure 3-4. block diagram of 8-bit timer (tm20) ti5/p75 f x /2 f x /2 3 f x /2 5 f x /2 7 f x /2 9 f x /2 11 internal bus internal bus coincidence 8-bit compare register 5 (cr5) level inversion selector selector 3 inv q s r inttm5 s r tcl52 tcl51 tcl50 timer clock select register 5 (tcl5) tce5 tmc56 lvs5 lvr5 tmc51 toe5 0 timer mode control register 5 (tmc5) ovf clear to5/p76 8-bit counter 5 (tm5) selector selector internal bus 8-bit compare register 20 (cr20) coincidence inttm20 f x /2 5 f x /2 11 selector clear 8-bit timer/counter 20 (tm20) 2 internal bus tce20 tcl201 tcl200 8-bit timer mode control register 20 (tmc20) selector
m pd178046, 178048 preliminary product information 21 figure 3-5. block diagram of 8-bit event counter (tm21) remark the 8-bit event counter (tm21) can be also used as an hsync counter. figure 3-6. block diagram of 8-bit remote control timer (tm9) internal bus 8-bit compare register 21 (cr21) coincidence inttm21 ti21/p73 selector clear 8-bit timer/counter 21 (tm21) 2 internal bus tce21 tcl211 tcl210 8-bit timer mode control register 21 (tmc21) selector inttm10 clear ti9/p77 8-bit timer register 9 (tm9) 8-bit timer capture register (cp91) internal bus 8-bit timer capture register (cp90) inttm11 inttm92 timer mode control register 9 (tmc9) 1/2 internal bus noise rejection rising edge detection noise rejection falling edge detection tce1 tcl2 tcl1 f x /2 6 f x /2 7 f x /2 8 f x /2 9 selector
m pd178046, 178048 22 preliminary product information figure 3-7. block diagram of watchdog timer 3.4 a/d converter an a/d converter with a resolution of 8 bits and 4 channels is provided. figure 3-8. block diagram of a/d converter internal bus osts2 osts1 osts0 wdcs2 wdcs1 wdcs0 run wdtm4 wdtm3 division mode select circuit output control circuit clock input control circuit divided clock select circuit run divider f x /2 8 intwdt reset wdt mode signal 3 watchdog timer clock select register (wdcs) oscillation stabilization time select register (osts) watchdog timer mode register (wdtm) ani0/p10 ani1/p11 ani2/p12 ani3/p13 sample & hold circuit voltage comparator tap selector control circuit control circuit v dd gnd0, gnd1 adcs3 intad power-fail comparison threshold value register 3 (pft3) voltage comparator pfen3 adcs3 ads33 ads32 ads31 ads30 0 fr32 fr31 fr30 0 0 0 pfcm3 pfhrm3 power-fail comparison mode register 3 (pfm3) a/d converter mode register 3 (adm3) analog input channel specification register 3 (ads3) 4 internal bus selector successive approxima- tion register (sar) a/d conversion result register (adcr3)
m pd178046, 178048 preliminary product information 23 3.5 serial interface two serial interface channels are provided. serial interface (iic1) serial interface (sio3) table 3-2. types and functions of serial interfaces function iic1 sio3 i 2 c bus mode (msb first) ? 3-wire serial i/o mode ? (msb first) figure 3-9. block diagram of serial interface (iic1) sda0/p22 sda1/p23 scl0/p20 scl1/p21 iic1 shift register 1 (iic1) stop condition/start condition/acknowledge detection circuit output latch serial clock counter interrupt request signal generation circuit intiic1 selector f x /2 4 f x /2 5 f x /2 6 f x /2 7 acknowledge output circuit serial clock control circuit control circuit control circuit control circuit control circuit
m pd178046, 178048 24 preliminary product information figure 3-10. block diagram of serial interface (sio3) 3.6 osd controller osd (on-screen display) is a function to display the channel number, volume, and time on the tv screen. user- programmable display patterns for osd are defied in the crom (character rom) area. the patterns actually displayed are stored in vram (video ram). figure 3-11. block diagram of osd controller internal bus 8 8 direction control circuit interrupt request signal generation circuit selector serial clock counter serial clock control circuit serial i/o shift register 3 (sio3) si3/p70 so3/p71 sck3/p72 intcsi3 f x /2 3 f x /2 5 f x /2 6 lc oscillation circuit synchro- nization protection circuit divider character rom (crom) output controller video ram (vram) address specification control data character pattern data osc1 osc2 oscmon/p74 h sync r g b black v sync
m pd178046, 178048 preliminary product information 25 3.7 pwm output four 8-bit pwm output channels and one 14-bit pwm output channel are provided. figure 3-12. block diagram of 8-bit pwm (pwm0) remark pwmsn: bit n of pwm output select register (pwms) n = 0 to 3 figure 3-13. block diagram of 14-bit pwm (pwm1) remark pwms4: bit 4 of pwm output select register (pwms) internal bus pwm 8-bit compare register 0n (pwmcr0n) pwm0n/p13n 8 8 f x 8-bit pwm counter 0 (pwmct0) ovf generation circuit iq c d c q s p13n output latch pwmsn internal bus pwm14-bit compare register 1 (pwmcr1) pwm1/p134 14 14 f x 14-bit pwm counter 1 (pwmct1) ovf generation circuit iq c d c q s p134 output latch pwms4
m pd178046, 178048 26 preliminary product information 4. interrupt function the following three types and 17 sources of interrupts are available: non-maskable : 1 note maskable : 16 note software : 1 note one of two types of interrupt sources (intwdt), non-maskable and maskable (internal) is selectable as the watchdog timer interrupt source. table 4-1. interrupt sources interrupt default interrupt source internal/ vector basic type priority note 1 external table configuration name trigger address type note 2 non- ? intwdt overflow of watchdog timer (when non-maskable internal 0004h (a) maskable interrupt is selected) maskable 0 intwdt overflow of watchdog timer (when interval timer mode (b) is selected) 1 intp0 detection of edge input to pin external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 inttm90 detection of 8-bit remote control timer (tm9) edge internal 000eh (b) 6 inttm91 0010h 7 intvsync detection of v sync signal edge external 0012h (c) 8 inttm21 generation of coincidence signal from 8-bit event internal 0014h (b) counter (tm21) 9 intiic1 end of transfer of serial interface (iic1) 0016h 10 inttm92 overflow of 8-bit remote control timer (tm9) 0018h 11 intcsi3 end of transfer of serial interface (sio3) 001ah 12 inttm5 generation of coincidence signal from 8-bit timer/event 001ch counter (tm5) 13 inttm20 generation of coincidence signal from 8-bit timer (tm20) 001eh 14 intbtm1 signal generation by basic timer (btm1) at 1- or 10-ms 0020h intervals 15 intad end of conversion of a/d converter 0022h software ? brk execution of brk instruction ? 003eh (d) notes 1. the default priority is used if two or more maskable interrupts occur at the same time. 0 is the highest and 15 is the lowest. 2. (a) through (d) in basic configuration type correspond to (a) through (d) in figure 4-1.
m pd178046, 178048 preliminary product information 27 figure 4-1. basic configuration of interrupt functions (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt internal bus interrupt request priority control circuit vector table address generation circuit standby release signal internal bus interrupt request if mk ie pr isp priority control circuit vector table address generation circuit standby release si g nal internal bus interrupt request if mk ie pr isp priority control circuit vector table address generation circuit standby release signal external interrupt mode registers (egp, egn) edge detection circuit
m pd178046, 178048 28 preliminary product information figure 4-1. basic configuration of interrupt functions (2/2) (d) software interrupt remark if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specification flag 5. rom correction the m pd178046 and 178048 allow part of the program in the mask rom to be replaced with a program in the internal expansion ram for execution. by using this rom correction function, bugs found in the mask rom can be removed and program flow can be changed. the rom correction function can be used at up to two places in the internal rom (program). internal bus interrupt request priority control circuit vector table address generation circuit
m pd178046, 178048 preliminary product information 29 6. standby function the standby function is used to reduce the current power consumption and can be used in the following two modes. halt mode : the operation clock of the cpu is stopped in this mode. the average current consumption can be reduced by using this mode in combination with the normal operation mode and operating intermittently. stop mode: the oscillation of the system clock is stopped in this mode. all the operations using the system clock are stopped and therefore, the current consumption can be substantially reduced. figure 6-1. standby function 7. reset function the m pd178046 and 178048 can be reset in the following three ways: external reset by using the reset pin internal reset by detecting hang-up time of the watchdog timer internal reset by means of power-on clear (poc) system clock operation stop mode system clock oscillation stops. halt mode clock supply to cpu stops but oscillation continues. stop instruction interrupt request interrupt request halt instruction
m pd178046, 178048 30 preliminary product information 8. instruction set (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz second #byte a r note sfr saddr !addr16 psw [de] [hl] [hl+byte] $addr16 1 none operand [hl+b] first [hl+c] operand a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] note except r = a
m pd178046, 178048 preliminary product information 31 second #byte a r note sfr saddr !addr16 psw [de] [hl] [hl+byte] $addr16 1 none operand [hl+b] first [hl+c] operand [hl] mov ror4 rol4 [hl+byte] mov [hl+b] [hl+c] x mulu c divuw note except r = a (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second #word ax rp note sfrp saddrp !addr16 sp none operand first operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, or hl
m pd178046, 178048 32 preliminary product information (3) bit manipulation instruction mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none operand first operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1 (4) call instruction/branch instruction call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second ax !addr16 !addr11 [addr5] $addr16 operand first operand basic br call callf callt br, bc, instruction br bnc bz, bnz compound bt, bf instruction btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
m pd178046, 178048 preliminary product information 33 9. package drawing i j g h f d n m cb m r 64 33 32 1 k l notes 1. controlling dimension millimeter. p64c-70-750a , c-3 item millimeters inches b c d f g h j k 1.778 (t.p.) 3.20.3 0.51 min. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.00.2 n 0 to 15 0.500.10 0.9 min. r 0.070 max. 0.020 0.035 min. 0.1260.012 0.020 min. 0.200 max. 0.750 (t.p.) 0.669 0.010 0.007 0 to 15 +0.004 e0.003 0.070 (t.p.) +0.10 e0.05 +0.004 e0.005 64 pin plastic shrink dip (750 mil) 2. each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. 3. item "k" to center of leads when formed parallel. a 58.0 2.283 +0.028 e0.008 +0.68 e0.20 i 4.05 0.159 +0.011 e0.008 +0.26 e0.20 a +0.009 e0.008
m pd178046, 178048 34 preliminary product information appendix a. development tools the following systems are available for developing a system using the m pd178046 and 178048. also refer to (5) note on using development tools . (1) language processor software ra78k/0 common 78k/0 series assembler package cc78k/0 common 78k/0 series c compiler package df178048 note device file for m pd178048 subseries cc78k/0-l common 78k/0 series c compiler library source file (2) flash memory writing tools flashpro ii dedicated flash pro product name pending note flash writing adapter (3) debugging tools ie-78k0-ns common 78k/0 series in-circuit emulator ie-70000-mc-ps-b power supply unit for ie-78k0-ns ie-70000-98-if-c interface adapter when pc-9800 series (except notebook type) is used as host machine ie-70000-cd-if pc card and interface cable when notebook type of pc-9800 series is used as host machine ie-70000-pc-if-c interface adapter when ibm pc/at tm or compatible machine is used as host machine ie-178048-ns-em1 note emulation board for emulating m pd178048 subseries product name pending note emulation probe for 64-pin plastic shrink dip id78k0-ns note integrated debugger for ie-78k0-ns sm78k0 common system simulator for 78k/0 series df178048 note device file for m pd178048 subseries note under development
m pd178046, 178048 preliminary product information 35 (4) real-time os rx78k/0 real-time os for 78k/0 series mx78k0 os for 78k/0 series (5) notes on using development tools use the id78k0-ns and sm78k0 with the df178048. use the rx78k/0 with the ra78k/0 and df178048. the flashpro ii, flash writing adapter (product name pending), and emulation probe (product name pending) are products of naito densei machida mfg. co., ltd. (tel (044) 822-3813). consult nec when purchasing these products. for a description of development tools from the third parties, refer to 78k/0 series selection guide (u11126e) . the host machine and os corresponding to each software package are as follows: host machine pc ews [os] pc-9800 series [japanese windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at and compatible machine sparcstation tm [sunos tm ] software [japanese/english windows] news (risc) tm [news-os tm ] ra78k/0 note cc78k/0 note id78k0-ns ? sm78k0 ? rx78k/0 note mx78k0 note note dos-based software
m pd178046, 178048 36 preliminary product information appendix b. related documents device-related documents document name document no. japanese english m pd178f048 preliminary product information u13056j planned m pd178048 subseries user?s manual planned planned 78k/0 series user?s manual - instruction u12326j u12326e 78k/0 series instruction set u10904j ? 78k/0 series instruction table u10903j ? m pd178048 subseries special function register table planned ? 78k/0 series application note fundamentals (i) u12704j iea-1288 documents on development tools (user?s manuals) document name document no. japanese english ra78k0 assembler package operation u11802j u11802e assembly language u11801j u11801e structured assembly language u11789j u11789e ra78k series structured assembler preprocessor u12323j eeu-1402 cc78k0 c compiler operation u11517j u11517e language u11518j u11518e cc78k0 c compiler application note programming know-how u13034j eea-1208 cc78k series library source file u12322j ? ie-78k0-ns planned planned ie-178048-ns-em1 planned planned sm78k0 system simulator windows based reference u10181j u10181e sm78k series system simulator external part user open u10092j 10092e interface specifications id78k0-ns integrated debugger pc based reference u12900j planned caution the contents of the above documents are subject to change without notice. be sure to use the latest edition of each document for designing.
m pd178046, 178048 preliminary product information 37 documents on embedded software (user?s manuals) document name document no. japanese english 78k/0 series real-time os fundamentals u11537j u11537e installation u11536j u11536e 78k/0 series os mx78k0 fundamentals u12257j u12257e other related documents document name document no. japanese english ic package manual c10943x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892j c11892e semiconductor device quality/reliability handbook c12769j under preparation microcomputer product series guide u11416j ? caution the contents of the above documents are subject to change without notice. be sure to use the latest edition of each document for designing.
m pd178046, 178048 38 preliminary product information windows and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or countries. pc/at is a trademark of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
m pd178046, 178048 preliminary product information 39 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j98. 2
no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the related documents referred to in this publication may include preliminary versions. however, preliminary versions are not marked as such. m pd178046, 178048

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